The present invention relates to an integrated circuit, such as a Programmable Logic Device (PLD) or a Field Programmable Gate Array (FPGA) where there is a source for a signal and a circuit and a nonvolatile reprogrammable switch comprising three transistors for selectively connecting the source to the circuit. The present invention also relates to a simplified nonvolatile reprogrammable switch.
PLDs or FPGAs are well-known in the art. Each type of device comprises a source for generating a signal and a circuit with a switch, such as an FET transistor, for selectively connecting the source to the circuit. Thus, the integrated circuit comprising of a PLD or an FPGA can be xe2x80x9cconfiguredxe2x80x9d to the user""s needs. This configuration can be done xe2x80x9con the flyxe2x80x9d in which the switch must be reconfigured every time the device is used. Alternatively, the configuration can be xe2x80x9cpermanentxe2x80x9d such as through the use of fuses and the like and the selective connection is made xe2x80x9cpermanent.xe2x80x9d Finally, this connection can also be reprogrammable using a nonvolatile memory cell as the storage element for controlling the FET transistor.
Heretofore, a nonvolatile memory cell, such as a cell using a floating gate to store charges in a stack gate configuration or in a split gate configuration is well-known in the art. However, in a typical nonvolatile memory cell, that is based upon a floating gate for storing of charges and with the charges stored on the floating gate controlling the conduction of current flow in a channel, the nonvolatile memory cell has a first region, and a spaced apart second region with a channel therebetween. The floating gate is positioned over and spaced apart from a portion of the channel for controlling the conduction of the charges in the channel. Heretofore, with the exception of the nonvolatile memory cell disclosed in U.S. Pat. No. 5,029,130, which is assigned to the present assignee and whose disclosure is incorporated herein in its entirety by reference, all of the other prior art nonvolatile memory cells require the use of a high voltage applied to one of the first region or the second region for programming, and applied to the other of the first region or the second region for erase. As a result, because high voltage must be applied to both the first region and to the second region during the erase operation and the programming operation, a nonvolatile memory cell used as a part of a reprogrammable nonvolatile memory switch has required the use of another transistor to separate the nonvolatile memory cell from the FET transistor. This addition of another transistor interposed between the nonvolatile memory cell and the FET transistor causes wastage in real estate in the silicon in that if a integrated circuit device has many interconnections requiring many reprogrammable nonvolatile memory switches, many excess transistors need to be used.
In U.S. Pat. No. 5,029,130, a nonvolatile memory cell is disclosed having a first region and a spaced apart second region with a channel therebetween. A floating gate is positioned over and spaced apart from a first portion of a channel which is adjacent to the first region. A control gate is positioned over and spaced apart from a second portion of the channel which is adjacent to the second region. In programming, the first region is supplied with a high positive voltage to attract electrons from the second region which are injected through the mechanism of hot electron injection onto the floating gate. During erase, the control gate is held at a xe2x80x9chighxe2x80x9d positive potential to attract electrons from the floating gate to Fowler-Nordheim tunnel through the insulation separating the control gate from the floating gate. The first and second regions can be held at ground or at floating.
An integrated circuit has a source for a signal and a circuit with a reprogrammable nonvolatile switch for selectively connecting the source for the signal to the circuit. The reprogrammable nonvolatile switch comprises a MOS transistor with a first terminal and a spaced apart second terminal and a channel in between the first terminal and the second terminal. A tunneling insulating layer is over the channel with a gate on the tunneling insulating layer and on the channel. The first terminal is connected to the source and the second terminal is connected to the circuit. A nonvolatile memory cell has a first region and a spaced apart second region with a channel therebetween. The first and second regions are of a first conductivity type with the channel being a second conductivity type. A first insulating layer is over the channel. A floating gate is on the first insulating layer and is spaced apart from a first portion of the channel. The first portion of the channel is adjacent to the first region. A control gate is on the first insulating layer and is spaced apart from a second portion of the channel. The second portion of the channel is adjacent to the second region. A second insulating layer is between the floating gate and the control gate. An FET transistor has a first terminal and a spaced apart second terminal with a channel therebetween. The first and second terminals of the FET transistor are of a second conductivity type with a channel being of the first conductivity type. A gate controls the flow of current between the first terminal and the second terminal. The gate of the FET transistor is connected to the floating gate. The first terminal is connected to a voltage source and the second terminal is connected to the second region of the non-volatile memory cell. The gate of the MOS transistor is connected to the second region of the nonvolatile memory cell. The first insulating layer permits the injection of charges from the channel onto the floating gate. The second insulating layer permits the Fowler-Nordheim tunneling of electrons between the floating gate and the control gate.